In today's computer market there is always constant evolution and turnover of different processors. Currently Intel's Core lines seem to be very popular and continue to set the standard in processor innovation (sorry AMD folks). There are two major versions of the Core line which are based on the newest Intel Nehalem architecture and are currently setting the standard in desktop performance.
The two lines which are currently released include the i5 and the i7 line of processors. The table at the bottom of the article cites the general specifications on these two lines. It is important to note that while the base speed of the processors themselves seems to be in line with past processors there have been a number of different innovations which are included in the current lines which make them outperform processors of the past.
All of these current processors are quad core; all support DDR3 RAM and all but one support hyper-threading which is the main difference between the current i5 and i7 lines. For those who don't know, hyper-threading is used by the processor to split the operations of each core into two virtual cores (or threads) and operate based on this eight virtual core structure.
Now another big difference between past processors and the current processors is the configuration of the North and South Bridges. In the past the Northbridge was used to interface the processor with the memory and graphics on the motherboard of the computer through the Front Side Bus (FSB). The Southbridge was used to connect to the slower interfaces including the I/O buses (PCI, PCIe, SATA, USB, and LAN among others) through an internal bus. The main problem with these relationships was with the speed of the FSB, in some circumstances the processor could process the data faster than the bus could deliver it producing a bottleneck.
The i5 and i7 processors interface with the memory and graphics hardware differently than had been done before. There are, however, two different methods which are currently used to perform these connections. The main similarity is that neither of the new methods uses a Northbridge as the memory connection functionality is built into the processor. These two different methods are implemented through the P(PM)55 and X58 chipsets.
The P(PM)55 chipset defines a dual-channel memory structure which currently runs at a speed of 10.6 GB/s per channel, allowing a max memory bandwidth of 21.2 GB/s. All PCIe graphics connections are built into the processor and provide up to 16 total 1GB/s lanes. It also creates a single chip architecture called the Platform Controller Hub (PCH) which is used to connect to all lower speed devices including USB, PCIe x1, LAN, Audio, and SATA. The connection between the processor and the P(PM)55 chipset is a Direct Media Interface (DMI) running at 2 GB/s.